1. Field of the Invention
The present invention relates to a semiconductor apparatus and, particularly, to a semiconductor apparatus having a shield line between a device and a line layer placed above the device.
2. Description of Related Art
A manufacturing process of semiconductor apparatus is recently moved to finer design rules. As the manufacturing process gets finer, the noise immunity of semiconductor apparatus decreases due to reduction of parasitic capacitance at a drain (drain capacitance) and shortening of a distance between lines.
One of the effects of the reduction in drain capacitance is a decrease in immunity against soft error that occurs due to cosmic radiation coming from the outside of semiconductor apparatus. One of the effects of the shortening of a distance between lines is signal interference between lines. The interference causes the signals that are transmitted through adjacent lines to appear as noise to each other, which leads to signal propagation error.
A technique to reduce the effects of the reduction in drain capacitance is disclosed in Japanese Unexamined Patent Application Publication No. 2005-183420 (which is referred to hereinafter as a related art). The related art aims to suppress the occurrence of soft error in an SRAM. FIG. 11 is a circuit diagram of an SRAM according to the related art. As shown in FIG. 11, the SRAM of the related art includes additional capacitors C1 and C2 respectively for nodes 101 and 102 (cross-coupling nodes) to store data. The additional capacitors C1 and C2 allow the capacitance of the nodes 101 and 102 to increase to thereby improve the soft error immunity.
Further, in the related art, a additional capacitor 130 is formed above an SRAM cell. FIG. 12 shows the layout of the SRAM according to the related art, and FIG. 13 shows the layout where the additional capacitor 130 is placed above an SRAM cell. As shown in FIG. 13, the capacitors C1 and C2 are appropriately placed in a layer above the SRAM cell in the related art. This eliminates the need for an additional area for the additional capacitors C1 and C2, which suppresses an increase in chip area.
However, the signal propagation error due to interference between lines is not addressed in the related art disclosed in Japanese Unexamined Patent Application Publication No. 2005-183420. In SRAM, a bit line is placed above the line to serve as a cross-coupling node. The voltage of the cross-coupling node has an amplitude between a power supply voltage VDD to a ground voltage VSS. Because the voltage of the cross-coupling node varies widely, the bit line placed above the cross-coupling node is subject to the effect (interference) of the voltage variation in the cross-coupling node. Thus, the voltage variation in the cross-coupling node can affect the bit line as noise.